*Strong DV knowldege (test plan development, test writing, SystemVerilog, UVM)
Write and augment existing test plans.
Implement test bench and scoreboards / checkers.
Implement test sequences as per plan and debug failures
Achieve 100% functional, code, and power coverage
Work closely with designers, micro architects & f/w to resolve issues
Ability to communicate & articulate clearly progress / issues with project leads
7+ years of proven experience as a DV engineer
Hands on Experience with executable test plans and Coverage Driven verification
Hands on experience with SV (SystemVerilog) and UVM (Universal Verification Methodology)
Hands on Experience with Synopsys VCS / Verdi or Cadence Incisive tools
Experience with UPF based simulation flow
2+ Years of experience with C/C++
Nice to Have:
Power and performance FPGA validation
Experience with Power Aware GLS flow
Tcl and Python (or similar) scripting language
ASIC design experience
Experience with complex SoCs
Must Have: Bachelor degree in Electrical/Computer Engineering or Computer Science
Master's Degree preferred but not required
Actalent connects passion with purpose. Our scalable talent solutions and services capabilities drive value and results and provide the expertise to help our customers achieve more. Every day, our experts around the globe are making an impact. We’re supporting critical initiatives in engineering and sciences that advance how companies serve the world. Actalent promotes consultant care and engagement through experiences that enable continuous development. Our people are the difference. Actalent is an operating company of Allegis Group, the global leader in talent solutions.
The company is an equal opportunity employer and will consider all applications without regards to race, sex, age, color, religion, national origin, veteran status, disability, sexual orientation, gender identity, genetic information or any characteristic protected by law.